1. Technical Field
Embodiments of the present disclosure generally relate to electronic device packages, to embedded packages including a multi-layered dielectric layer, and methods of manufacturing the same.
2. Related Art
Electronic devices employed in electronic systems may include various circuit elements such as active elements and/or passive elements. The circuit elements may be integrated in and/or on a semiconductor substrate, thereby constituting the electronic device (also, referred to as a semiconductor chip or a semiconductor die). The electronic device may be mounted on a printed circuit board (PCB) or a package substrate to produce an electronic device package. The package substrate may include circuit interconnections such as silicon interposers. The electronic device package may be mounted on a main board to constitute the electronic systems, for example, computers, mobile systems, or data storage media.
The electronic devices may be buried in a substrate using device embedding technologies. According to the device embedding technologies, the electronic devices may be buried in a dielectric layer constituting the package substrate, and interconnections may be formed on a surface of the dielectric layer. As the semiconductor chips (or the electronic devices) become more highly integrated, sizes of the interconnections formed on the dielectric layer of the package substrate have been gradually reduced and connection structures electrically connecting the semiconductor chips to the interconnections have also been reduced. If the interconnections on the package substrate and the connection structures in the package substrate are reduced in size or dimension, the minimization of the interconnections and the connection structures may be more influenced by a surface roughness of the dielectric layer.
In the embedded packages fabricated using the device embedding technologies, the dielectric layer (or a dielectric film) may contain fillers to improve a mechanical characteristic and/or a thermal characteristic of the dielectric layer. The fillers may lower the coefficient of thermal expansion (CTE) of the dielectric layer and may be introduced into the dielectric layer to enhance the rigidity or the hardness of the dielectric layer. If the fillers are contained in the dielectric layer, the surface roughness of the dielectric layer may be affected by the fillers. Increase of the surface roughness of the dielectric layer may lead to a difficulty in scaling down the interconnections which are formed on the dielectric layer.